manuais Compaq 21264

Compaq 21264 Manual do Utilizador (356 páginas)

Marca: Compaq | Categoria: Hardware | Tamanho: 3.99 MB |

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Índice

Reference Manual

1

Table of Contents

3

3 Hardware Interface

4

9 Electrical Data

8

10 Thermal Management

8

A Alpha Instruction Set

9

Glossary

10

Preface

17

Terminology and Conventions

19

Abbreviation Meaning

20

Term Words Bytes Bits Other

21

UNDEFINED

22

UNPREDICTABLE

22

Introduction

25

1–2 Introduction

26

Data Type Description

26

Introduction 1–3

27

Internal Architecture

29

21264/EV67 Microarchitecture

31

Internal Architecture 2–7

35

2.1.1.9 Retire Logic

36

Internal Architecture 2–9

37

Floating-Point

38

Execution Units

38

2.1.5.2 Data Cache

40

2.2 Pipeline Organization

41

Pipeline Organization

42

2.3 Instruction Issue Rules

44

Instruction Issue Rules

45

2.3.2 Ebox Slotting

46

2.3.3 Instruction Latencies

48

2.4 Instruction Retire Rules

49

2–22 Internal Architecture

50

Instruction Type Notes

51

2.7.1 Load Hit Speculation

52

Symbol Meaning

53

2.7.3 CMOV Instruction

54

Internal Architecture 2–27

55

Internal Architecture 2–29

57

2.10 Instruction Ordering

58

2.11 Replay Traps

59

• RdBlk, RdBlkMod, RdBlkI

60

Internal Architecture 2–33

61

2–34 Internal Architecture

62

2–36 Internal Architecture

64

Name Extent Type Description

64

UNFD UNDZ Result

65

Bits Meaning

65

2.15.1 AMASK

66

2.15.2 IMPLVER

66

2.16 Design Examples

67

Design Examples

68

Hardware Interface

69

Signal Type Definition

71

Signal Type Count Description

71

3–4 Hardware Interface

72

3–6 Hardware Interface

74

3.3 Pin Assignments

76

Pin Assignments

77

Mechanical Specifications

85

FM-05644-EV6

86

FM-05645-EV6

87

Cache and External Interfaces

89

4.1.1 System Interface

91

4.3 Bcache Structure

95

4.4 Victim Data Buffer

96

4.5 Cache Coherency

96

(Sheet 1 of 2)

97

CMD SysDc 21264/EV67 Action

99

Cache Coherency

100

4.6 Lock Mechanism

102

4.7 System Port

104

System Port

105

4.7.1 System Port Pins

105

• SYS_FDBK_EN[7:0]

106

• SYS_CLK_LD_VECTOR[15:0]

106

• SYS_BPHASE_LD_VECTOR[3:0]

106

21264/EV67

128

Command NXM

128

4.8 Bcache Port

130

Bcache Port

131

4.8.1 Bcache Port Pins

131

4.8.2 Bcache Clocking

132

4.8.3 Bcache Transactions

135

4.8.4 Pin Descriptions

139

4.9 Interrupts

142

Internal Processor Registers

143

Mbox IPRs

144

5.1 Ebox IPRs

145

VPTB[63:30]

146

VA_FORM_32

146

B_ENDIAN

146

Ebox IPRs

147

VA[47:13]

148

INVAL_ITB[47:13]

149

PC[63:2]

150

VA[31:13]

151

Ibox IPRs

152

IPR Index Bit Register Field

163

5.3 Mbox IPRs

167

SMC[1:0]

171

SPE[2:0]

171

5.4 Cbox CSRs and IPRs

174

Cbox CSRs and IPRs

175

6.1 PALcode Description

185

6.2 PALmode Environment

186

6.4.1 HW_LD Instruction

187

Opcodes Reserved for PALcode

188

6.4.2 HW_ST Instruction

188

6.4.3 HW_RET Instruction

189

6.5.1 IPR Scoreboard Bits

192

6.5.4 IPR Access Ordering

193

6.6 PALshadow Registers

195

6.8 PALcode Entry Points

196

Entry Name Type Offset

197

Description

197

6.9.1 DTB Fill

198

Processor I Processor J

199

6.9.2 ITB Fill

200

Performance Counter Support

202

6.10.1 General Precautions

202

Operation Function

209

7.1.3 PLL Ramp Up

214

7.2 Fault Reset Flow

216

SromOE_L

217

ClkFwdRst_H

217

7.4 Warm Reset Flow

219

7.5 Array Initialization

220

7.10 Reset State Machine

224

Reset State Machine

225

7.11.2 PLL Output Clocks

227

Dividers

228

8.3 Dcache Tag Parity Error

230

8.5 Dcache Store Second Error

232

8.7 Bcache Tag Parity Error

233

8.11 Double-Bit Fill Errors

237

8.12 Error Case Summary

237

Error Case Summary

238

Electrical Data

241

9.2 DC Characteristics

242

DC Characteristics

243

9.4 AC Characteristics

246

AC Characteristics

247

Thermal Management

251

Operating Temperature

252

10.2 Heat Sink Specifications

253

Heat Sink Specifications

254

Thermal Design Considerations

257

Testability and Diagnostics

259

11.3 IEEE 1149.1 Port

261

Scan SequenceScan Sequence

262

11.5.1 Built-in Self-Test

263

11.5.2 SROM Initialization

263

Alpha Instruction Set

267

Alpha Instruction Summary

268

A.2 Reserved Opcodes

274

A.6 Opcode Summary

278

Alpha Instructions

281

21264/EV67 Hardware

281

Supplied Result Exception

281

A–16 Alpha Instruction Set

282

B.1 Boundary-Scan Register

285

Boundary-Scan Register

286

296

Modify-Write

307

IVA_FORM, and EXC_SUM

309

D.11 Restriction 14 : HW_RET

309

Guideline 16 : JSR-BAD VA

310

Lock Flag

311

IC_FLUSH_ASM, CLEAR_MAP

312

HW_MFPR IPR_MM_STAT

313

LDQ rx, (ry)

313

p6 ; past stall in palmode

314

Handlers

320

Data Pin Usage

324

Tag Pin Usage

324

E.3 Dual-Data Rate SSRAMs

325

Dual-Data Rate SSRAMs

326

Glossary

327

Glossary–2

328

Glossary–4

330

Glossary–6

332

Glossary–8

334

Glossary–10

336

Glossary–12

338

Glossary–14

340

Glossary–16

342

Glossary–18

344

Numerics

345

Index–10

354

Index–11

355

Index–12

356

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